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ISL6115A
Data Sheet February 25, 2009 FN6855.0
12V Power Distribution Controllers
This fully featured hot swap power controller targets +12V applications. The ISL6115A with its integrated charge pump has a higher (6.5V vs 5V) gate drive than its sister part the ISL6115 making this part an immediate efficiency improvement replacement. This IC features programmable overcurrent (OC) detection, current regulation (CR) with time delay to latch-off and softstart. The current regulation level is set by 2 external resistors; RISET sets the CR Vth and the other is a low ohmic sense element across, which the CR Vth is developed. The CR duration is set by an external capacitor on the CTIM pin, which is charged with a 20A current once the CR Vth level is reached. If the voltage on the CTIM capacitor reaches 1.9V the IC then quickly pulls down the GATE output latching off the pass FET.
Features
* HOT SWAP Single Power Distribution Control for +12V * Overcurrent Fault Isolation * Programmable Current Regulation Level * Programmable Current Regulation Time to Latch-Off * Rail-to-Rail Common Mode Input Voltage Range * Enhanced Internal Charge Pump Drives N-Channel MOSFET gate to 6.5V above IC bias. * Undervoltage and Overcurrent Latch Indicators * Adjustable Turn-On Ramp * Protection During Turn-On * Two Levels of Overcurrent Detection Provide Fast Response to Varying Fault Conditions * 1s Response Time to Dead Short * Pb-Free (RoHS Compliant)
Ordering Information
PART NUMBER ISL6115AIBZ ISL6115AIBZ-T* ISL6115ACBZ PART TEMP. PACKAGE PKG. MARKING RANGE (C) (Pb-free) DWG. # 6115A IBZ 6115A IBZ 6115A CBZ -40 to +85 -40 to +85 0 to +70 0 to +70 8 Ld SOIC 8 Ld SOIC 8 Ld SOIC 8 Ld SOIC M8.15 M8.15 M8.15 M8.15
Applications
* Power Distribution Control * Hot Plug Components and Circuitry
ISL6115ACBZ-T* 6115A CBZ
Pinout
ISL6115A (8 LD SOIC) TOP VIEW
ISET ISEN GATE VSS 1 2 3 4 8 7 6 5 PWRON PGOOD CTIM VDD
ISL6115AEVAL1Z Evaluation Platform *Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Application Circuits- High Side Controller
+ LOAD -
1 2 3 4
8
ISL6115A
PWRON 7 6 OC 5 PGOOD
+V SUPPLY TO BE CONTROLLED
+12V
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL6115A Simplified Block Diagram
VDD + + ISET + + VREF ISEN ENABLE 12V PGOOD UV 8V POR QN Q R R S PWRON
UV DISABLE OC + -
20A CLIM
7.5k + + 1.86V 20A RISING EDGE PULSE CTIM
GATE 10A
FALLING EDGE DELAY 18V ENABLE
+ WOCLIM
VSS
18V
VDD
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FN6855.0 February 25, 2009
ISL6115A Pin Descriptions
PIN # SYMBOL 1 2 3 4 5 6 ISET ISEN GATE VSS VDD CTIM FUNCTION Current Set Current Sense External FET Gate Drive Pin Chip Return Chip Supply Current Limit Timing Capacitor Power Good Indicator 12V chip supply. This can be either connected directly to the +12V rail supplying the switched load voltage or to a dedicated VSS +12V supply. Connect a capacitor from this pin to ground. This capacitor determines the time delay between an overcurrent event and chip output shutdown (current limit time-out). The duration of current limit time-out is equal to 93k x CTIM. Indicates that the voltage on the ISEN pin is satisfactory. PGOOD is driven by an open drain N-Channel MOSFET and is pulled low when the output voltage (VISEN) is less than the UV level for the particular IC. PWRON is used to control and reset the chip. The chip is enabled when PWRON pin is driven high to a maximum of 5V or is left open. Do not drive this input >5V. After a current limit time-out, the chip is reset by a low level signal applied to this pin. This input has 20A pull-up capability. DESCRIPTION Connect to the low side of the current sense resistor through the current limiting set resistor. This pin functions as the current limit programming pin. Connect to the more positive end of sense resistor to measure the voltage drop across this resistor. Connect to the gate of the external N-Channel MOSFET. A capacitor from this node to ground sets the turn-on ramp. At turn-on this capacitor will be charged to VDD +6.5V by an 14A current source.
7
PGOOD
8
PWRON Power-ON
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FN6855.0 February 25, 2009
ISL6115A
Absolute Maximum Ratings TA = +25C
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +16V GATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD + 8V ISEN, PGOOD, PWRON, CTIM, ISET. . . . . . . -0.3V to VDD + 0.3V
Thermal Information
Thermal Resistance (Typical, Note 1) JA (C/W) 8 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . 98 Maximum Junction Temperature (Plastic Package) . . . . . . . +150C Maximum Storage Temperature Range . . . . . . . . . .-65C to +150C Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
VDD Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . +12V 15% Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -40C to +85C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES: 1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 2. All voltages are relative to GND, unless otherwise specified. 3. Limits should be considered typical and are not production tested.
Electrical Specifications
VDD = 12V, TA = TJ = full temperature range, Unless Otherwise Specified. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
PARAMETER CURRENT CONTROL ISET Current Source ISET Current Source Current Limit Amp Offset Voltage Current Limit Amp Offset Voltage GATE DRIVE GATE Response Time to Severe OC GATE Response Time to Overcurrent GATE Turn-On Current GATE Pull-Down Current GATE Pull-Down Current (Note 3) Undervoltage Threshold GATE High Voltage BIAS VDD Supply Current VDD POR Rising Threshold VDD POR Falling Threshold VDD POR Threshold Hysteresis Maximum PWRON Pull-Up Voltage PWRON Pull-Up Voltage PWRON Rising Threshold PWRON Hysteresis PWRON Pull-Up Current
IISET_ft IISET_pt Vio_ft Vio_pt TJ = +15C to +55C VISET - VISEN VISET - VISEN, TJ = +15C to +55C
17 19 -4.5 -2
20 20 0 0
22 21 4.5 2
A A mV mV
pd_woc_amp pd_oc_amp IGATE OC_GATE_I_4V WOC_GATE_I_4V 12VUV_VTH 12VG
VGATE to 10.8V VGATE to 10.8V VGATE to = 6V Overcurrent Severe Overcurrent
10.8 45 8.9
100 600 14 82 0.8 9.6
16.7 124 10.2 -
ns ns A mA A V V
GATE Voltage
VDD + 5.7V VDD + 6.5V
IVDD VDD_POR_L2H VDD_POR_H2L VDD_POR_HYS PWRN_PUV PWRN_V PWR_Vth PWR_hys PWRN_I VDD Low to High VDD High to Low VDD_POR_L2H - VDD_POR_H2L Maximum External Pull-up Voltage PWRON Pin Open
7 6.9 0.1 2.5 1.1 125 12.6
3 8.4 8.1 0.3 5 3.2 1.7 170 17
3.9 9 8.7 0.5 2.35 250 24
mA V V V V V V mV A
CURRENT REGULATION DURATION/POWER GOOD CTIM Charging Current CTIM Fault Pull-Up Current (Note 3) Current Limit Time-Out Threshold Voltage Power Good Pull Down Current CTIM_Vth PG_Ipd CTIM Voltage VOUT = 0.5V CTIM_ichg0 VCTIM = 0V 17.2 1.6 20.5 20 1.8 8 25 2.1 A mA V mA
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FN6855.0 February 25, 2009
ISL6115A Description and Operation
The ISL6115A is targeted for +12V single power supply distribution control for generic hot swap switching applications. This ICs features a highly accurate programmable current regulation (CR) level with programmable time delay to latch-off, and programmable soft-start turn-on ramp all set with a minimum of external passive components. It also includes severe OC protection that immediately shuts down the MOSFET switch should a rapid load current transient such as with a dead short cause the CR Vth to exceed the programmed level by 150mV. Additionally, it has an UV indicator and an OC latch indicator. The functionality of the PGOOD feature is enabled once the IC is biased, monitoring and reporting any UV condition on the ISEN pin. Upon initial power-up, the IC can either isolate the voltage supply from the load by holding the external N-Channel MOSFET switch off or apply the supply rail voltage directly to the load for true hot swap capability. The PWRON pin must be pulled low for the device to isolate the power supply from the load by holding the external N-Channel MOSFET off. With the PWRON pin held high or floating the IC will be in true hot swap mode. In both cases the IC turns on in a soft-start mode protecting the supply rail from sudden inrush current. At turn-on, the external gate capacitor of the N-Channel MOSFET is charged with a 11A current source resulting in a programmable ramp (soft-start turn-on). The internal ISL6115A charge pump supplies the gate drive for the 12V supply switch driving that gate to ~VDD +6.5V. Load current passes through the external current sense resistor. When the voltage across the sense resistor exceeds the user programmed CR voltage threshold value, (see Table 1 for RISET programming resistor value and resulting nominal current regulation threshold voltage, VCR) the controller enters its current regulation mode. At this time, the time-out capacitor, on CTIM pin is charged with a 20A current source and the controller enters the current limit time to latch-off period. The length of the current limit time to latch-off duration is set by the value of a single external capacitor (see Table 2) for CTIM capacitor value and resulting nominal current limited time-out to latch-off duration placed from the CTIM pin (pin 6) to ground. The programmed current level is held until either the OC event passes or the time-out period expires. If the former is the case then the N-Channel MOSFET is fully enhanced and the CTIM capacitor is discharged. Once CTIM charges to ~1.8V signaling that the time-out period has expired, an internal latch is set whereby the FET gate is quickly pulled to 0V turning off the N-Channel MOSFET switch, isolating the faulty load.
TABLE 1. RISET PROGRAMMING RESISTOR VALUE RISET RESISTOR 10k 4.99k 2.5k 1.25k NOTE: Nominal Vth = RISET x 20A. TABLE 2. CTIM CAPACITOR VALUE CTIM CAPACITOR 0.022F 0.047F 0.1F NOMINAL CURRENT LIMITED PERIOD 2ms 4.4ms 9.3ms NOMINAL CR VTH 200mV 100mV 50mV 25mV
NOTE: Nominal time-out period = CTIM x 93k.
This IC responds to a severe overcurrent load (defined as a voltage across the sense resistor >150mV over the OC Vth set point) by immediately driving the N-Channel MOSFET gate to 0V in about 10s. The gate voltage is then slowly ramped up turning on the N-Channel MOSFET to the programmed current regulation level; this is the start of the time-out period. Upon a UV condition, the PGOOD signal will pull low when connected through a resistor to the logic or VDD supply. This pin is a UV fault indicator. For an OC latch-off indication, monitor CTIM, pin 6. This pin will rise rapidly from 1.8V to VDD once the time-out period expires. See Figures 2 through 13 for graphs and waveforms related to text. The IC is reset after an OC latch-off condition by a low level on the PWRON pin and is turned on by the PWRON pin being driven high.
Application Considerations
Design applications where the CR Vth is set extremely low (25mV or less), there is a two-fold risk to consider. * There is the susceptibility to noise influencing the absolute CR Vth value. This can be addressed with a 100pF capacitor across the RSET resistor. * Due to common mode limitations of the overcurrent comparator, the voltage on the ISET pin must be 20mV above the IC ground either initially (from ISET*RSET) or before CTIM reaches time-out (from gate charge-up). If this does not happen, the IC may incorrectly report overcurrent fault at start-up when there is no fault. Circuits with high load capacitance and initially low load current are susceptible to this type of unexpected behavior. Do not signal nor pull-up the PWRON input to > 5V. Exceeding 6V on this pin will cause the internal charge pump to malfunction. During the soft-start and the time-out delay duration with the IC in its current limit mode, the VGS of the external N-Channel MOSFET is reduced driving the MOSFET switch into a (linear
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FN6855.0 February 25, 2009
ISL6115A
region) high rDS(ON) state. Strike a balance between the CR limit and the timing requirements to avoid periods when the external N-Channel MOSFETs may be damaged or destroyed due to excessive internal power dissipation. Refer to the MOSFET SOA information in the manufacturer's data sheet. When driving particularly large capacitive loads a longer soft-start time to prevent current regulation upon charging and a short CR time may offer the best application solution relative to reliability and FET MTF. Physical layout of RSENSE resistor is critical to avoid the possibility of false overcurrent occurrences. Ideally, trace routing between the RSENSE resistors and the IC is as direct and as short as possible with zero current in the sense lines (see Figure 1).
.
CORRECT
INCORRECT
TO ISEN AND RISET
CURRENT SENSE RESISTOR
FIGURE 1. SENSE RESISTOR PCB LAYOUT
Typical Performance Curves
3.5 3.4 3.3 3.2 3.1 3.0 2.9 2.8 -40 0 70 25 85 TEMPERATURE (C) 125 ISET (A) Idd (mA) 22.0 21.5 21.0 20.5 20.0 19.5 19.0 18.5 18.0 -40 0 25 70 TEMPERATURE (C) 85 125
FIGURE 2. VDD BIAS CURRENT
FIGURE 3. ISET SOURCE CURRENT
20.8 CTIM CHARGE CURRENT (A) 20.6 20.4 20.2 20.0 19.8 19.6 19.4 19.2 19.0 18.8 -40 0 25 70 TEMPERATURE (C) 85 125 CTIM - 0V CTIM VTH (V)
1.82 1.81 1.80 1.79 1.78 1.77
-40
0
25 70 TEMPERATURE (C)
85
125
FIGURE 4. CTIM CURRENT SOURCE
FIGURE 5. CTIM OC VOLTAGE THRESHOLD
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FN6855.0 February 25, 2009
ISL6115A Typical Performance Curves
9.80
(Continued)
GATE TURN-ON CURRENT (A) 16.0 15.5 15.0 14.5 14.0 13.5 13.0 12.5 12.0 -40 0 25 70 TEMPERATURE (C) 85 125
9.75 UVTH (V)
9.70
9.65
9.60
-40
0
25
70
85
125
TEMPERATURE (C)
FIGURE 6. UV THRESHOLD
FIGURE 7. GATE CHARGE CURRENT
8.3 POWER ON RESET (V) 8.2 8.1 8.0 7.9 7.8 7.7 7.6 7.5 -40 VDD HI TO LO 0 25 70 TEMPERATURE (C) 85 125 GATE VOLTAGE (V) VDD LO TO HI
22 21 20 19 18 17 16 15 14 13 9 10 11 12 13 BIAS VOLTAGE (V) 14 15 -40C +25C +85C
FIGURE 8. POWER-ON RESET VOLTAGE THRESHOLD
FIGURE 9. GATE VOLTAGE vs BIAS and TEMPERATURE
PWRON
PWRON
GATE GATE
PGOOD PGOOD
VOUT
VOUT
FIGURE 10. ISL6115A TURN-ON
FIGURE 11. ISL6115A TURN-OFF
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FN6855.0 February 25, 2009
ISL6115A Typical Performance Curves
ILOAD
(Continued)
ILOAD
GATE
GATE VOUT VOUT CTIM CTIM
FIGURE 12. IOC REGULATION and TURN-OFF
FIGURE 13. WOC TURN-OFF and RESTART
ISL6115AEVAL1Z Board
The ISL6115AEVAL1Z is default provided as a +12V high side switch controller with the CR level set at ~2.5A. See Figure 11 for ISL6115AEVAL1Z schematic and Table 3 for BOM. Bias and load connection points are provided along with test points for each IC pin. With J1 installed the ISL6115A will be biased from the +12V supply (VIN) being switched. Connect the load to VLOAD+. PWRON pin pulls high internally enabling the ISL6115A if not driven low via PWRON test point or J2.
VLOAD+ VOUT R3 1 R1 2 3 U1 R2 C1 J1 VIN +12V VBIAS VBIAS 4 ISL6115A U2 8 7 6 5 C3 C2 R4 AGND
With R3 = 1.24k the CR Vth is set to 24.8mV and with the 10m sense resistor (R1) the ISL6115AEVAL1Z has a nominal CR level of 2.5~A. The 0.01F delay time to latch-off capacitor results in a nominal 1ms before latch-off of output after an OC event. Reconfiguring the ISL6115AEVAL1Z board for a higher CR level can be done by changing the RSENSE and/or RISET resistor values as the provided FET is rated for a much higher current.
J2 PWRON PGOOD CTIM
FIGURE 14. ISL6115AEVAL1Z HIGH SIDE SWITCH APPLICATION and PHOTOGRAPH
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FN6855.0 February 25, 2009
ISL6115A
TABLE 3. BILL OF MATERIALS, ISL6115AEVAL1Z COMPONENT DESIGNATOR U1 R1 R2 R3 R4 C1 C2 C3 J1 J2 N-FET Load Current Sense Resistor Gate Stability Resistor COMPONENT NAME COMPONENT DESCRIPTION 11.5m, 30V, 11.5A Logic Level N-Channel Power MOSFET or equivalent WSL-2512 10m 1W Metal Strip Resistor 20 0603 Chip Resistor
Overcurrent Voltage Threshold Set Resistor 1.24k 0603 Chip Resistor (Vth = 24.8mV) PGOOD Pull up Resistor Gate Timing Capacitor IC Decoupling Capacitor Time Delay Set Capacitor Bias Voltage Selection Jumper PWRON Disable 10k 0603 Chip Resistor 0.001F 0402 Chip Capacitor (<2ms) 0.1F 0402 Chip Capacitor 0.01F 0402 Chip Capacitor (1ms) Install if switched rail voltage is = +12V. Remove and provide separate +12V bias voltage to U2 via VBIAS if ISL6116, ISL6117 or ISL6120 is being evaluated. Install J2 to disable U2. Connects PWRON to GND.
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FN6855.0 February 25, 2009
ISL6115A Small Outline Plastic Packages (SOIC)
N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45 H 0.25(0.010) M BM
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1
L
MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 MAX 1.75 0.25 0.51 0.25 5.00 4.00 NOTES 9 3 4 5 6 7 8 Rev. 1 6/05
MIN 0.0532 0.0040 0.013 0.0075 0.1890 0.1497
MAX 0.0688 0.0098 0.020 0.0098 0.1968 0.1574
B C D E
A1 0.10(0.004) C
e H h L N
0.050 BSC 0.2284 0.0099 0.016 8 0 8 0.2440 0.0196 0.050
1.27 BSC 5.80 0.25 0.40 8 0 6.20 0.50 1.27
e
B 0.25(0.010) M C AM BS
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
a
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 10
FN6855.0 February 25, 2009

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